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philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 3-311 1996 aug 15 description the philips 8xc453 is an i/o expanded single-chip microcontroller fabricated with philips high-density cmos technology. philips epitaxial substrate minimizes latch-up sensitivity. the 8xc453 is a functional extension of the 87c51 microcontroller with three additional i/o ports and four i/o control lines. the 8xc453 is available in 68-pin lcc packages. four control lines associated with port 6 facilitate high-speed asynchronous i/o functions. the 87c453 includes an 8k 8 eprom, a 256 8 ram, 56 i/o lines, two 16-bit timer/counters, a seven source, two priority level, nested interrupt structure, a serial i/o port for either a full duplex uart, i/o expansion, or multi-processor communications, and on-chip oscillator and clock circuits. the 87c453 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the ram contents. features ? 80c51 based architecture ? seven 8-bit i/o ports ? port 6 features: eight data pins four control pins direct mpu bus interface isa bus interface parallel printer interface ibf and obf interrupts a flag latch on host write ? on the microcontroller: 8k 8 eprom quick pulse programming algorithm two-level program security system 256 8 ram two 16-bit counter/timers two external interrupts ? external memory addressing capability 64k rom and 64k ram ? low power consumption: normal operation: less than 24ma at 5v, 16mhz idle mode power-down mode ? reduced emi ? full-duplex enhanced uart framing error detection automatic address recognition lcc pin functions lcc 9161 10 26 60 44 27 43 pin function 1ea /v pp 2 p2.0/a8 3 p2.1/a9 4 p2.2/a10 5 p2.3/a11 6 p2.4/a12 7 p2.5/a13 8 p2.6/a14 9 p2.7/a15 10 p0.7/ad7 11 p0.6/ad6 12 p0.5/ad5 13 p0.4/ad4 14 p0.3/ad3 15 p0.2/ad2 16 p0.1/ad1 17 p0.0/ad0 18 v cc 19 p4.7 20 p4.6 21 p4.5 22 p4.4 23 p4.3 pin function 24 p4.2 25 p4.1 26 p4.0 27 p1.0 28 p1.1 29 p1.2 30 p1.3 31 p1.4 32 p1.5 33 p1.6 34 p1.7 35 rst 36 p3.0/rxd 37 p3.1/txd 38 p3.2/into 39 p3.3/int1 40 p3.4/t0 41 p3.5/t1 42 p3.6/wr 43 p3.7/rd 44 p5.0 45 p5.1 46 p5.2 pin function 47 p5.3 48 p5.4 49 p5.5 50 p5.6 51 p5.7 52 xtal2 53 xtal1 54 v ss 55 ods 56 ids 57 bflag 58 aflag 59 p6.0 60 p6.1 61 p6.2 62 p6.3 63 p6.4 64 p6.5 65 p6.6 66 p6.7 67 psen 68 ale/prog su00157
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-312 ordering information eprom 1 romless rom temperature c and package freq. (mhz) pkg. dwg # p87c453ebaa otp p80C453ebaa p83c453ebaa 68pin plastic leaded chip carrier, 0 to +70 3.5 to 16 sot188-3 p87c453efaa otp p80C453efaa p83c453efaa 68pin plastic leaded chip carrier, 40 to +85 3.5 to 16 sot188-3 p87c453eblka uv 68-pin ceramic leaded chip carrier with window, 0 to +70 3.5 to 16 1473a p87c453eflka uv 68-pin ceramic leaded chip carrier with window, 40 to +85 3.5 to 16 1473a note: 1. otp = one-time programmable eprom. uv = erasable eprom. logic symbol port 0 port 1 port 2 port 3 address and data bus address bus rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 port 6 port 4 port 5 port 6 control ods ids bflag aflag su00085
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-313 block diagram psen ea v pp ale/prog rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register 256 bytes ram port 0 latch port 2 latch register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr pcon scon tmod tcon th0 tl0 th1 tl1 sbuf ie ip interrupt, serial port and timer blocks p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 port 4 drivers port 4 latch p4.0p4.7 port 5 drivers port 5 latch p5.05.7 port 6 latch port 6 drivers p6.0p6.7 port 6 control/status ids ods aflag bflag 8k x 8 eprom psw csr dph dpl auxr su00158
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-314 pin description mnemonic pin no. type name and function v ss 54 i ground: 0v reference. v cc 18 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 17-10 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 is also the multiplexed data and low-order address bus during accesses to external memory. external pull-ups are required during program verification. port 0 can sink/source eight ls ttl inputs. p1.0p1.7 27-34 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 receives the low-order address bytes during program memory verification. port 1 can sink/source three ls ttl inputs, and drive cmos inputs without external pull-ups. p2.0p2.7 2-9 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 emits the high-order address bytes during access to external memory and receives the high-order address bits and control signals during program verification. port 2 can sink/source three ls ttl inputs, and drive cmos inputs without external pull-ups. p3.0p3.7 36-43 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 can sink/source three ls ttl inputs, and drive cmos inputs without external pull-ups. port 3 also serves the special functions listed below: 36 i rxd (p3.0): serial input port 37 o txd (p3.1): serial output port 38 i int0 (p3.2): external interrupt 39 i int1 (p3.3): external interrupt 40 i t0 (p3.4): timer 0 external input 41 i t1 (p3.5): timer 1 external input 42 o wr (p3.6): external data memory write strobe 43 o rd (p3.7): external data memory read strobe p4.0p4.3 p4.0p4.7 26-19 i/o i/o port 4: port 4 is an 8-bit bidirectional i/o port with internal pull-ups. port 4 can sink/source three ls ttl inputs and drive cmos inputs without external pull-ups. p5.0p5.7 44-51 i/o port 5: port 5 is an 8-bit bidirectional i/o port with internal pull-ups. port 5 can sink/source three ls ttl inputs and drive cmos inputs without external pull-ups. p6.0p6.7 59-66 i/o port 6: port 6 is a specialized 8-bit bidirectional i/o port with internal pull-ups. this special port can sink/source three ls ttl inputs and drive cmos inputs without external pull-ups. port 6 can be used in a strobed or non-strobed mode of operation. port 6 works in conjunction with four control pins that serve the functions listed below: ods 55 i ods : output data strobe ids 56 i ids : input data strobe bflag 57 i/o bflag: bidirectional i/o pin with internal pull-ups aflag 58 i/o aflag: bidirectional i/o pin with internal pull-ups rst 35 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal pull-down resistor permits a power-on reset using only an external capacitor connected to v cc . ale/prog 68 i/o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. ale is activated at a constant rate of 1/6 the oscillator frequency except during an external data memory access, at which time one ale is skipped. ale can sink/source three ls ttl inputs and drive cmos inputs without external pull-ups. this pin is also the program pulse during eprom programming. psen 67 o program store enable: the read strobe to external program memory. psen is activated twice each machine cycle during fetches from external program memory. however, when executing out of external program memory, two activations of psen are skipped during each access to external program memory. psen is not activated during fetches from internal program memory. psen can sink/source eight ls ttl inputs and drive cmos inputs without an external pull-up. this pin should be tied low during programming. ea /v pp 1 i instruction execution control/programming supply voltage: when ea is held high, the cpu executes out of internal program memory, unless the program counter exceeds 1fffh. when ea is held low, the cpu executes out of external program memory. ea must never be allowed to float. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. xtal1 53 i crystal 1: input to the inverting oscillator amplifier that forms the oscillator. this input receives the external oscillator when an external oscillator is used. xtal2 52 o crystal 2: an output of the inverting amplifier that forms the oscillator. this pin should be floated when an external oscillator is used.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-315 table 1. 87c453 special function registers symbol description direct address bit names and addresses msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ef ee ed ec eb ea e9 e8 csr*# port 6 command/status e8h mb1 mb0 ma1 ma0 obfc idsm obf ibf fch dptr data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h bf be bd bc bb ba b9 b8 ip* interrupt priority b8h pob pib ps pt1 px1 pt0 px0 x0000000b auxr# auxiliary register 8eh af ao x0000000b af ae ad ac ab aa a9 a8 ie* interrupt enable a8h ea iob iib es et1 ex1 et0 ex0 00000000b p0* port 0 80h 87 b6 85 84 83 82 81 80 ffh p1* port 1 90h 97 96 95 94 93 92 91 90 ffh p2* port 2 a0h a7 a6 a5 a4 a3 a2 a1 a0 ffh p3* port 3 b0h b7 b6 b5 b4 b3 b2 b1 b0 ffh p4*# port 4 c0h c7 c6 c5 c4 c3 c2 c1 c0 ffh p5*# port 5 c8h cf ce cd cc cb ca c9 c8 ffh p6*# port 6 d8h df de dd dc db da d9 d8 ffh pcon power control 87h smod1 smod0 pof 1 gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tmod timer/counter mode 89h gate c/t m1 m0 gate c/t m1 m0 00h th0 timer 0 high byte 8ch 00h th1 timer 1 high byte 8dh 00h tl0 timer 0 low byte 8ah 00h tl1 timer 1 low byte 8bh 00h notes: * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. reset value depends on reset source.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-316 ie.0 ie.2 int0 it0 tf0 int1 it1 tf1 ri ti ie register ip register high priority interrupt interrupt polling sequence low priority interrupt individual enables global disable 0 1 0 1 ibf su00562 ie.1 ie.3 ie.4 ie.5 obf ie.6 figure 1. 8xc453 interrupt control system ex0 lsb msb bit symbol function ie.7 ea disables all interrupts. if ea=0, no interrupt will be acknowledged. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ie.6 iob enables or disables the output buffer full (obf) interrupt. if iob=0, the interrupt is disabled, if iob=1, an interrupt will occur if ea is set and data has been read from the output buffer register through port 6 by the external host pulsing ods low. ie.5 iib enables or disables the input buffer full (ibf) interrupt. if iib=0, the interrupt is disabled. if iib=1, an interrupt will occur if ea is set and data has been written into the port 6 input data buffer by the host strobing ids low. ie.4 es enables or disables the serial port interrupt. if es=0, the serial port interrupt. if es=0, the serial port interrupt is disabled. ie.3 et1 enables or disables the timer 1 overflow interrupt. if et1=0, the timer 1 interrupt is disabled. ie.2 ex1 enables or disables external interrupt 1. if ex1=0, external interrupt 1 is disabled. ie.1 et0 enables or disables the timer 0 overflow interrupt. if et0=0, the timer 0 interrupt is disabled. ie.0 ex0 enables or disables external interrupt 0. if ex0=0, external interrupt 0 is disabled. su00563 et0 ex1 et1 es iib iob ea figure 2. 8xc453 interrupt enable (ie) register
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-317 px0 lsb msb bit symbol function ip.7 e reserved. ip.6 pob defines the output buffer full interrupt (iob) priority level. pob=1 programs it to the higher priority level. ip.5 pib defines the input buffer full interrupt (iib) priority level. pib=1 programs it to the higher priority level. ip.4 ps defines the serial port interrupt priority level. ps=1 programs it to the higher priority level. ip.3 pt1 defines the timer 1 interrupt priority level. pt1=1 programs it to the higher priority level. ip.2 px1 defines the external interrupt 1 priority level. px1=1 programs it to the higher priority level. ip.1 pt0 enables or disables the timer 0 interrupt priority level. pt0=1 programs it to the higher prior- ity level. ip.0 px0 defines the external interrupt 0 priority level. px0=1 programs it to the higher priority level. su00564 pt0 px1 pt1 ps pib pob e figure 3. 8xc453 interrupt priority (ip) register idl pcon (87h) bit symbol function pcon.7 smod1 double baud rate bit. when set to a 1 and timer 1 is used to generate baud rate, and the serial port is used in modes 1, 2, or 3. pcon.6 smod0 if set to 1, scon.7 will be the framing error bit (fe). if pcon.6 is cleared, scon.7 will be sm0. pcon.5 e reserved. pcon.4 pof power off flag is set during power on of v cc . if then cleared by software, it can be used to determine if a warm start has occurred. pcon.3 gf1 general-purpose flag bit. pcon.2 gf0 general-purpose flag bit. pcon.1 pd power-down bit. setting this bit activates power-down mode. it can only be set if input ew is high. pcon.0 idl idle mode bit. setting this bit activates the idle mode. if logic 1s are written to pd and idl at the same time, pd takes precedence. su00565 pd gf0 gf1 pof e smod2 smod1 0 1 2 3 4 5 6 7 figure 4. power control register (pcon)
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-318 scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0 is located at pcon6. **f osc = oscillator frequency su00043 bit: 76543210 figure 5. serial port control register (scon) smod1 smod0 osf pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su00044 figure 6. uart framing error detection
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-319 sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 7. uart multiprocessor communication, automatic address recognition special function register addresses special function register addresses for the device are identical to those of the 80c51, except for the additional registers listed in table 2. enhanced uart the uart operates in all of the usual modes that are described in the first section of this book for the 80c51. in addition the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the 87c453 uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 5). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 6. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 7. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to b used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-320 in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are teated as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature. the 87c453 uart has all of the capabilities of the standard 80c51 uart plus framing error detection and automatic address recognition. as in the 80c51, all four modes of operation are supported as well as the 9th bit in modes 2 and 3 that can be used to facilitate multiprocessor communication. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. idle mode in the idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power down mode can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values until the power down mode is terminated. on the 87c453 either a hardware reset or external interrupt can cause an exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power down the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. power off flag the power off flag (pof) in pcon is set by on-chip circuitry when the v cc level on the 87c453 rises from 0 to 5v. the pof bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. the v cc level must remain above 3v for the pof to remain unaffected by the v cc level. design consideration ? when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once ? mode the once (aon-circuit emulationo) mode facilitates testing and debugging of systems using the 87c453 without having to remove the ic from the circuit. the once mode is invoked by: 1. pull ale low while the device is in reset and psen is high; 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the 87c453 is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. ports 4 and 5 ports 4 and 5 are bidirectional i/o ports with internal pull-ups. port 4 is an 8-bit port. port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. ports 4 and 5 are addressed at the special function register addresses shown in table 2. port 6 port 6 is a special 8-bit bidirectional i/o port with internal pull-ups (see figure 8). this port can be used as a standard i/o port, or in strobed modes of operation in conjunction with four special control lines: ods , ids , aflag, and bflag. port 6 operating modes are controlled by the port 6 control status register (csr). port 6 and the csr are addressed at the special function register addresses shown in table 2. the following four control pins are used in conjunction with port 6: ods output data strobe for port 6. ods can be programmed to control the port 6 output drivers and the output buffer full flag (obf), or to clear only the obf flag bit in the csr (output-always mode).
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-321 ods is active low for output driver control. the obf flag can be programmed to be cleared on the negative or positive edge of ods . can produce an iob interrupt (see figure 2). ids input data strobe for port 6. ids is used to control the port 6 input latch and input buffer full flag (ibf) bit in the csr. the input data latch can be programmed to be transparent when ids is low and latched on the positive transition of ids , or to latch only on the positive transition of ids . correspondingly, the ibf flag is set on the negative or positive transition of ids . can produce an iib interrupt (see figure 2). aflag aflag is a bidirectional i/o pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. aflag can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. this feature grants complete port 6 status to external devices. bflag bflag is a bidirectional i/o pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. bflag can also be programmed to input an enable signal for port 6. when bflag is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the ids strobe when bflag is high. both features are enabled when bflag is low. this feature facilitates the use of the 87c453 in bused multiprocessor systems. control status register the control status register (csr) establishes the mode of operation for port 6 and indicates the current status of port 6 i/o registers. all control status register bits can be read and written by the cpu, except bits 0 and 1, which are read only. reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see table 3). csr.0 input buffer full flag (ibf) (read only) the ibf bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of ids . this can occur on the negative or positive edge of ids , as determined by csr.2. when ibf is set, the interrupt enable register bit iib (ie.5) is set. the interrupt service routine vector address for this interrupt is 002bh. ibf is cleared when the cpu reads the input buffer register. csr.1 output buffer full flag (obf) (read only) the obf flag is set to a logic 1 when the cpu writes to the port 6 output data buffer. obf is cleared by the positive or negative edge of ods , as determined by csr.3. when obf is cleared, the interrupt enable register bit iob (ie.6) is set. the interrupt service routine vector address for this interrupt is 0033h. csr.2 ids mode select (idsm) when csr.2 = 0, a low-to-high transition on the ids pin sets the ibf flag. the port 6 input buffer is loaded on the ids positive edge. when csr.2 = 1, a high-to-low transition on the ids pin sets the ibf flag. port 6 input buffer is transparent when ids is low, and latched when ids is high. csr.3 output buffer full flag clear mode (obfc) when csr.3 = 1, the positive edge of the ods input clears the obf flag. when csr.3 = 0, the negative edge of the ods input clears the obf flag. csr.4, csr.5 aflag mode select (ma0, ma1) bits 4 and 5 select the mode of operation for the aflag pin as follows: ma1 ma0 aflag function 0 0 logic 0 output 0 1 logic 1 output 1 0 obf flag output (csr.1) 1 1 select (sel) input mode the select (sel) input mode is used to determine whether the port 6 data register or the control status register is output on port 6. when the select feature is enabled, the aflag input controls the source of port 6 output data. a logic 0 on aflag input selects the port 6 data register, and a logic 1 on aflag input selects the control status register. the value of the aflag input is latched into the auxiliary register (auxr) bit 1 (auxr.1). checking this bit (af) will allow the 87c453's program to determine if port 6 was loaded with data or a upi command. csr.6, csr.7 bflag mode select (mb0, mb1) bits 6 and 7 select the mode operation as follows: mb1 mb0 bflag function 0 0 logic 0 output 0 1 logic 1 output 1 0 ibf flag output (csr.0) 1 1 port enable (pe ) in the port enable mode, ids and ods inputs are disabled when bflag input is high. when the bflag input is low, the port is enabled for i/o. reduced emi mode the onchip clock distribution drivers have been identified as the cause of most of the emi emissions from the 80c51 family. by tailoring the clock drivers properly, a compromise between maximum operating speed and minimal emi emissions can be achieved. typically, an order in magnitude of reduction is possible over previous designs. this feature has been implemented on this chip along with the additional capability of turning off the ale output. setting the ao bit (auxr.0) in the auxr special function register will disable the ale output. reset forces a 0 into auxr.0 to enable normal 80c51 type operation. auxiliary register (auxr) 76543210 af ao latched value of aflag when port 6 inputs data from ids strobe 0 = ale enabled 1 = ale disabled
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-322 internal bus ids mode input buffer (p6 read) output drivers bflag/ods mode (csr.6/.7) aflag mode (csr.4/.5) mux control/status register (csr) output buffer (p6 write) input buffer full (csr.0) output buffer full (csr.1) edge/level select (csr.2) ids ods bflag aflag port 6 su00087 figure 8. port 6 block diagram table 2. special function register addresses register address bit address name symbol address msb lsb port 4 p4 c0 c7 c6 c5 c4 c3 c2 c1 c0 port 5 p5 c8 cf ce cd cc cb ca c9 c8 port 6 data p6 d8 df de dd dc db da d9 d8 port 6 control status csr e8 ef ee ed ec eb ea e9 e8 slave address saddr a9 slave address mask saden b9 auxiliary register auxr 8e table 3. control status register (csr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mb1 mb0 ma1 ma0 obfc idsm obf ibf bflag mode select aflag mode select output buffer flag clear mode input data strobe mode output buffer flag full input buffer flag full 0/0 = logic 0 output* 0/1 = logic 1 output* 1/0 = ibf output 1/1 = pe input (0 = select) (1 = disable i/o) 0/0 = logic 0 output* 0/1 = logic 1 output* 1/0 = obf output 1/1 = sel input (0 = select) (1 = control/status) 0 = negative edge of ods 1 = positive edge o ods 0 = positive edge of ids 1 = low level of ids 0 = output data buffer empty 1 = output data buffer full 0 = input data buffer empty 1 = input data buffer full note: * output-always mode: mb1 = 0, ma1 = 1, and ma0 = 0. in this mode, port 6 is always enabled for output. ods only clears the obf flag.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-323 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 40 to +85 c storage temperature range 65 to +150 c voltage on any other pin to v ss 0.5 to +6.5 v power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteristics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. voltages are with respect to v ss unless otherwise noted. dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v test limits symbol parameter conditions min typ 1 max unit v il input low voltage; ports 0, 1, 2, 3, 4, 5, 6, ids , ods , aflag, bflag; except ea 0.5 0.2v cc 0.1 v v il1 input low voltage to ea 0 0.2v cc 0.3 v v ih input high voltage; except xtal1, rst 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage; xtal1, rst 0.7v cc v cc +0.5 v v ol output low voltage; ports 1, 2, 3, 4, 5, 6, aflag, bflag i ol = 1.6ma 2 0.45 v v ol1 output low voltage; port 0, ale, psen i ol = 3.2ma 2 0.45 v v oh output high voltage; ports 1, 2, 3, 4, 5, 6, aflag, bflag i oh = 60 m a, i oh = 25 m a i oh = 10 m a 2.4 0.75v cc 0.9v cc v v v v oh1 output high voltage (port 0 in external bus mode, ale, psen ) 3 i oh = 800 m a, i oh = 300 m a i oh = 80 m a 2.4 0.75v cc 0.9v cc v v v i il logical 0 input current,; ports 1, 2, 3, 4, 5, 6 v in = 0.45v 50 m a i tl logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6 see note 4 650 m a i li input leakage current; port 0 v in = v il or v ih 10 m a i cc power supply current: active mode @ 16mhz 5 idle mode @ 16mhz 5 power down mode see note 6 11.5 1.3 3 25 4 50 ma ma m a r rst internal reset pull-down resistor 50 300 k w c io pin capacitance 7 plcc package 10 pf notes: 1. typical ratings are based on a limited number of samples from early manufacturing lots, and not guaranteed. values are room temp., 5v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and the other ports. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input.. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address bits are stabilizing. 4. pins of ports 1, 2, 3, 4, 5 and 6 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 5. i cc max at other frequencies is given by: active mode: i cc max = 0.94 x freq + 13.71 idle mode: i cc max = 0.14 x freq +2.31 where freq is the external oscillator frequency in mhz. i cc max is given in ma. see figure 20. 6. see figures 21 through 24 for i cc test conditions. 7. c io applies to ports 1 through 6, ids , ods , aflag, bflag, xtal1, xtal2.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-324 ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10%, v ss = 0v 16mhz clock variable clock symbol figure parameter min max min max unit 1/t clcl oscillator frequency 3.5 16 mhz t lhll 9 ale pulse width 85 2t clcl 40 ns t avll 9 address valid to ale low 22 t clcl 40 ns t llax 9 address hold after ale low 32 t clcl 30 ns t lliv 9 ale low to valid instruction in 150 4t clcl 100 ns t llpl 9 ale low to psen low 32 t clcl 30 ns t plph 9 psen pulse width 142 3t clcl 45 ns t pliv 9 psen low to valid instruction in 82 3t clcl 105 ns t pxix 9 input instruction hold after psen 0 0 ns t pxiz 9 input instruction float after psen 37 t clcl 25 ns t aviv 9 address to valid instruction in 207 5t clcl 105 ns t plaz 9 psen low to address float 10 10 ns data memory t rlrh 10, 11 rd pulse width 275 6t clcl 100 ns t wlwh 10, 11 wr pulse width 275 6t clcl 100 ns t rldv 10, 11 rd low to valid data in 147 5t clcl 165 ns t rhdx 10, 11 data hold after rd 0 0 ns t rhdz 10, 11 data float after rd 65 2t clcl 60 ns t lldv 10, 11 ale low to valid data in 350 8t clcl 150 ns t avdv 10, 11 address to valid data in 397 9t clcl 165 ns t llwl 10, 11 ale low to rd or wr low 137 239 3t clcl 50 3t clcl +50 ns t avwl 10, 11 address valid to wr low or rd low 122 4t clcl 130 ns t qvwx 10, 11 data valid to wr transition 13 t clcl 50 ns t whqx 10, 11 data hold after wr 13 t clcl 50 ns t rlaz 10, 11 rd low to address float 0 0 ns t whlh 10, 11 rd or wr high to ale high 23 103 t clcl 40 t clcl +40 ns shift register t xlxl 12 serial port clock cycle time 750 12t clcl ns t qvxh 12 output data setup to clock rising edge 492 10t clcl 133 ns t xhqx 12 output data hold after clock rising edge 8 2t clcl 117 ns t xhdx 12 input data hold after clock rising edge 0 0 ns t xhdv 12 clock rising edge to input data valid 492 10t clcl 133 ns port 6 input (input rise and fall times = 5ns) t flfh 15 pe width 209 3t clcl +20 ns t ilih 15 ids width 209 3t clcl +20 ns t dvih 15 data setup to ids high or pe high 0 0 ns t ihdz 15 data hold after ids high or pe high 30 30 ns t ivfv 16 ids to bflag (ibf) delay 130 130 ns
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-325 ac electrical characteristics (continued) 16mhz clock variable clock symbol figure parameter min max min max unit port 6 output t oloh 13 ods width 209 3t clcl +20 ns t fvdv 14 sel to data out delay 85 85 ns t oldv 13 ods to data out delay 80 80 ns t ohdz 13 ods to data float delay 35 35 ns t ovfv 13 ods to aflag (obf) delay 100 100 ns t fldv 13 pe to data out delay 120 120 ns t ohfh 14 ods to aflag (sel) delay 100 100 ns external clock t chcx 17 high time 20 20 ns t clcx 17 low time 20 20 ns t clch 17 rise time 20 20 ns t chcl 17 fall time 20 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-326 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t pliv t lhll t plph t lliv t plaz t llpl t aviv su00056 figure 9. external program memory read cycle t llax ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a0a15 from pch t whlh t lldv t llwl t rlrh t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00007 figure 10. external data memory read cycle
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-327 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx su00008 figure 11. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 figure 12. shift register mode timing
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-328 t ovfv t ohdz t oldv obf (aflag) pe (bflag) ods port 6 t ovfv t oloh t fldv su00088 figure 13. port 6 output t fvdv t fvdv t ohfh ods sel (aflag) port 6 data data csr su00089 figure 14. port 6 select mode t ihdz pe (bflag) ids port 6 t flfh t ilih t dvih su00090 figure 15. port 6 input t ivfv t ivfv ibf (bflag) ids su00091a figure 16. ibf flag output
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-329 v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 17. external clock drive v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 18. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 19. float waveform 30 25 20 15 10 5 4mhz 8mhz 12mhz 16mhz freq at xtal1 max active mode typ active mode max idle mode typ idle mode i cc ma valid only within frequency specifications of the device under test. su00092 figure 20. i cc vs. freq
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-330 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal ods v cc ids su00093 figure 21. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal ods v cc ids su00094 figure 22. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 23. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) ods v cc ids su00095 figure 24. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-331 eprom characteristics the 87c453 is programmed by using a modified quick-pulse programming ? algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the 87c453 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an 87c453 manufactured by philips semiconductors. table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 25 and 26. figure 27 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 26. note that the 87c453 is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 25. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 2 and 3 specified in table 4 are held at the `program code data' levels indicated in table 4. the ale/prog is pulsed low 15 to 25 times, as shown in figure 26. to program the encryption table, repeat the 15 to 25 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the lock bits, repeat the 15 to 25 pulse programming sequence using the `pgm lock bit' levels. after one lock bit is programmed, further programming of the code memory and encryption table is disabled. however, the other lock bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 1 and 2 as shown in figure 27. the other pins are held at the `verify code data' levels indicated in table 4. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low. the values are: (030h) = 15h indicates manufactured by philips (031h) = b9h indicates 87c453 program/verify algorithms any algorithm in agreement with the conditions listed in table 4, and which satisfies the timing specifications, is suitable. erasure characteristics erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. for this and secondary effects, it is recommended that an opaque label be placed over the window. for elevated temperature or environments where solvents are being used, apply kapton tape fluorglas part number 23455, or equivalent. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15w-sec/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1s state. table 4. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p3.7 p3.6 read signature 1 0 1 1 0 0 0 0 program code data 1 0 0* v pp 1 0 1 1 verify code data 1 0 1 1 0 0 1 1 pgm encryption table 1 0 0* v pp 1 0 1 0 pgm lock bit 1 1 0 0* v pp 1 1 1 1 pgm lock bit 2 1 0 0* v pp 1 1 0 0 notes: 1. `0' = valid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75v 0.25v. 3. v cc = 5v 10% during programming and verification. * ale/prog receives 15 to 25 programming pulses while v pp is held at 12.75v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. ? trademark phrase of intel corporation.
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-332 a0a7 1 1 1 46mhz +5v pgm data +12.75v 15 to 25 100 m s pulses to ground 0 1 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87c453 su00159 figure 25. programming configuration ale/prog: ale/prog: 1 0 1 0 15 to 25 pulses 100 m s+ 10 10 m s min su00160 figure 26. prog waveform a0a7 1 1 1 46mhz +5v pgm data 1 1 0 0 enable 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87c453 su00161 figure 27. program verification
philips semiconductors preliminary specification 80C453/83c453/87c453 cmos single-chip 8-bit microcontrollers 1996 aug 15 3-333 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 28) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p1.0p1.7 p2.0p2.4 port 0 ale/prog ea /v pp p2.7 enable su00020 t ehsh note: * for programming verification see figure 25. for verification conditions see figure 27. figure 28. eprom programming and verification

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